| 摘要: | IC 晶圓的製造已進入病毒尺寸(90~22 nm)，ㄧ個不及1 公分平方的芯片(core)可佈滿超過 人類總數65 億的MOS 電晶體，其電晶體密度已高於世界人口的密度。在奈米製程下，連線 延遲主導系統的效能，衍生在實體設計上的很多效應，如製程變異、漏電流、信號完整度及 製造可靠度等問題，更激勵實體設計的更多考量。對一顆系統晶片SoC 而言，時脈網路(clock network)結構主導了整體SoC 系統的功率消耗與效能，它可由一個或多個時脈信號源來整合 與分流所有IP 與模組的同步動作，因此，時脈延遲(clock delay)、偏移或傾斜誤差(skew)及功 率消耗等將決定此顆SoC 晶片的執行效能與穩定度。因應低功率動作必是時勢所趨，多重電 壓(multiple voltages)或叢聚電壓(cluster voltages)供應需求之平面規劃(floorplanning)與佈局 (palacement)就成為降低及節省功率之實體設計必要措施，對時脈網路而言，則形成了時脈島 網路 (clock island network)。我們觀察現有已發表的論文，其平面規劃或佈局結果有關每一 個電壓島的分佈區域總是不規則的，如rectilinear area 或跨越區域等，如何設計一個時脈合成 系統來驅動多重電壓的時脈島網路， 及考量與結合可製造性設計(design for manufacturability，DFM)之實體效應，如減低天線效應(antenna effect reduction)、光學鄰接校 正(optical proximity correction)、沉餘穿孔點加入(redundant via insertion)、虛擬金屬層加入 (dummy metal/via insertion)輔助化學機械研磨(chemical mechanical polishing)、及緩衝器/位準 轉換器插入與閘時脈(gated-clock)控制功率消耗管理等解決方法，此即為提出本計畫的目的。 第一年計劃研究重點：我們首先收集已發表的平面規劃與佈局之電壓島的分佈圖樣組成 測試例子或標準例子，含整體功率消耗及時序的限制等參數，再粹取每個電壓島的虛擬不規 則區域(virtual rectilinear area)及在此區域的clock sinks 等所需的參數，同時，定義一個 rectilinear area 限制區域之X 時脈樹建置的問題及多重電壓島時脈網路的X 架構時脈繞線建 置的問題。接著將初步研究之四層X 架構時脈繞線，擴充與考量不同連線延遲模型之估算， 進行每個電壓島不規則區域限制下個別的subclock tree 的建置，進一步藉由相關的結果如時 脈延遲、時脈偏移及功率消耗等來評估X 架構時脈繞線品質，且配合緩衝器或重複器插入及 調整元件大小來有效縮短時脈延遲、保持零時脈偏移及降低功率消耗等。進階時，可考量具 有障礙物(obstacles)存在於rectilinear 區域內的障礙物避免(obstacle avoidance) 之X 架構時脈 樹建置。完成各個電壓島的時脈樹後，再進一步組合成整體系統的多電壓島時脈樹之建構， 且因應不同的叢聚電壓，還須考量位準電壓轉換器(level-shifter converter)的插入，使時脈信 號位準驅動達到正確性，且須規劃插入位準電壓轉換器為最少量，以節省功率消耗。最後， 配合多電壓島供應，並結合閘時脈(gated-clock) 技術控制以達到功率消耗管理的設計方法。 上述方法對所有test cases 與 benchmarks 作不同情況改善前與改善後的測試與實驗，將此結 果作分析與比較，甚至於作綜合改良。 第二年計劃研究重點：延續第一年獲得的經驗與累積成果，將單一或多重電壓島之X 架 構時脈繞線，考量結合奈米製程下可製造性設計之單一實體效應的影響，且限制增加時脈延 遲與確保零時脈偏移及低功率消耗原則。首先，結合X 架構時脈繞線與天線效應避免(antenna effect avoidance)之後置處理，分析不同奈米製程參數、線寬與線長所可能引發之出天線效應， 完成天線效應避免與控制加入跳線數量的最小化；其次，結合X 架構時脈繞線與光學鄰接校 2 正(optical effect correction) 之後置處理，檢測與修正因OPE 可能引起不完整圖像繞線部分； 接著，結合X 架構時脈繞線與冗餘穿孔點加入(redundant via insertion) 之後置處理，檢測與 修正可能引起良率缺陷繞線部分，並控制冗餘穿孔插入數量的合理化；進而結合X 架構時脈 繞線與虛擬金屬層加入(dummy metal/via insertion)之後置處理，改進化學機械研磨(chemical mechanical polishing)所要求之均化佈線密度(wire density)，但須防止寄生電容所衍生的串音效 應(crosstalks)。再進一步，考量結合X 架構時脈繞線與任兩種以上可製造性設計實體效應之 組合，並找出它們之間可能存在的互助性與互斥性之影響。最後，我們具體延申與考量多重 電壓島間時脈樹是否存在著耦合電容和互感等串音干擾，並分析此干擾對時脈延遲、時脈偏 移與功率消耗等影響，提出抑制與解決方法；也嘗試開發X 架構平面化時脈繞線(planar X-clock routing)，以單層或使用非常少量金屬線來完成X 架構平面化時脈繞線。上述方法對 所有test cases 與 benchmarks 作不同情況改善前與改善後的測試與實驗，將此結果作分析與 比較，甚至於作綜合改良。 綜合連續兩年的所持續規劃研究計畫工作，相信此應用研究成果將對學術界與產業界會 有某種程度的貢獻。
The IC design in wafer process have getting into the virus size, such as 90~22nm. Within 1 cm2 of core chip, there is over 6.5 billion transistors which number is just the total population in a world. The transistor density in a core has larger than the population density. In nanometer process, the delay of interconnects has dominated system performance of a chip. Effects in physical design are derived due to advanced process, such as problems of process variation, signal integrity, leakage current, and design for manufacturing (DFM). These effects derive that we need more correction in physical design steps whereas we design a chip. For a SoC (system-on a chip), the clock network construction dominates system performance and power consumption. A system consists of one or more clocks that integrate all IPs and modules for clocking synchronization. Clock delay, clock skew, and power consumption dominate the performance and stability of a SoC. Currently, low power in a SoC is one of major requirements. Thus, multiple voltages or cluster voltages in power supply have applied to designs of floorplanning and placement for reducing power consumption. Consequently, there are a number of clock island networks in the environment of multiple voltage islands. We observe number of published papers related to floorplannings and placements that the distribution of voltage islands of their results are always nonuniform. That is, the surrounding of an island is a rectilinear area. How to design a clock synthesized system to construct an X-architecture-based clock tree for driving clock island networks in the environment of multiple voltage islands. Moreover, associate with the effects in physical DFM issues, such as antenna effect reduction, optical proximity correction, redundant vias insertion, dummy metal/via insertion for chemical mechanical polishing, and buffer/lever-shifter insertion combined with gated-clock control for managing power, into the clock synthesized system. Solving them is the purpose of our proposal. The works of first year in this proposal, we first collect all results based on voltage-island floorplannings and placements in recently published papers. According to the island distribution of their results, we create or organize some test cases or benchmarks by extracting the rectilinear area for a voltage island or multiple islands. Thus, we can define problems of X-clock tree construction for a voltage island or multi-voltage islands. For the clock problem in a rectilinear area with some clock sinks, we first expand proposed 4-layer X-clock routing algorithm with a delay model to apply to the problem to obtain an initial result. The algorithm can improve performance by the evaluation in terms of delay, skew, and power. Buffer (repeater) insertion associated with sizing buffers to reduce clock delay and power but keep zero skew. Advancely, the above problem can extend to consider some obstacles in a rectilinear area and the X-clock tree construction needs to have obstacle avoidance. After completing all one-island X-clock trees, then we integrate them to be an X-clock tree appropriated for the multi-island clock network of a SoC chip. To respone multi-voltage supply, level-shifter converters are required to insert into positions from low-to-high voltages in an X-clock tree for maintaing clock working normally. Moreover, number of level-shifter converters should be controlled to minimum for power reduction. In addition, a 2 gated-clock strategy can manage power consumption in advance. All test cases and benchmarks are used for evaluating our above approaches of X-based clock routing and, furthermore, improve proposed approaches for well-defined comparisons. The works of second year, with initial results in first year, we associate with the effects in physical DFM issues into our X-clock tree construction for a voltage island or multi-voltage islands. First, combine X-clock tree with antenna effect avoidance for post refinement. The number of inserted jumpers in the clock tree should be minimal for maximally reducing antenna effects. Then, combine X-clock tree with optical proximity correction for post refinement. All optical proximity errors in wires of the tree should be detected and corrected by modifying wire shapes or reassigning layers. Furthermore, combine X-clock tree with redundant vias insertion for post refinement. All vias are assumped to be possiblly defected for trying to insert at least one redundant via for yield rate. Moreover, combine X-clock tree with dummy metal or via insertion for post refinement. Inserting dummy metals or vias is for unifying layout density for improving chemical mechanical polishing, but crosstalk avoidance should be protected for inserted wires/vias that they are possiblly too closer with each other. Finally, Then, we mix at least two effects in physical design of DFM issues with X-clock tree for post refinement. We observe the mutuality of their effects for improvement. Furthermore, we consider crosstalk between multi-voltage clock islands in advance and propose the solution for crosstalk avoidance. And, we attempt to investigate a planar X-based clock routing for reducing the usage of number of metal layers, the challenge is how to complete the planar X-clock tree in a limited area. All test cases and benchmarks are used for evaluating our above approaches of X-based clock routing and, furthermore, improve proposed approaches for well-defined comparisons. Approaches of two-year proposal associated with overall DFM issues to X-architecture clock tree construction in the environment of multi-voltage clock islands are valuable to investigate. We believe that proposed approaches to all above problems of X-clock routing synthesis will have valuable contribution for academic and industrial areas. |
