| 摘要: | 因應低功率動作已是時勢所趨，多重電壓(multiple voltages)或叢聚電壓(cluster voltages)供應需求 之平面規劃(floorplanning)與佈局(palacement)就成為降低及節省功率之實體設計必要措施，對一顆系 統晶片SoC 的時脈網路而言，則形成了時脈島網路 (clock island network) ，其時脈延遲(clock delay)、 時脈偏移或傾斜誤差(skew)及功率消耗等將決定此顆SoC 晶片的執行效能與穩定度。我們觀察現有已 發表的論文，其平面規劃或佈局結果有關每一個電壓島的分佈區域總是不規則的，如rectilinear area 或跨越區域等，如何設計一個時脈合成系統來驅動多重電壓的時脈島網路，及考量與結合可製造性設 計(design for manufacturability，DFM)之實體效應，如減低天線效應(antenna effect reduction)、光學鄰 接校正(optical proximity correction)、沉餘穿孔點加入(redundant via insertion)、虛擬金屬層加入(dummy metal/via insertion)輔助化學機械研磨(chemical mechanical polishing)、及緩衝器/位準轉換器插入與閘時 脈(gated-clock)控制功率消耗管理等解決方法，此即為提出本計畫的目的。 第一年計劃研究重點：定義一個Divide-and-Conquer 為主的多重電壓島X 架構時脈網路建置的問 題，延續我們執行中之電壓島型態的時脈樹建置方法，對所有test cases 與 benchmarks 作至少兩個電 壓島型態的測試與實驗，再解析與比較時脈延遲、時脈偏移、功率消耗及插入位準電壓轉換器數量等 之差異，甚至於作綜合改良。同時，定義一個rectilinear area 限制區域之X 時脈樹建置的問題，接著 將初步研究之X 架構時脈繞線擴充與考量不同連線延遲模型之估算，進行每個電壓島不規則區域限制 下個別的subclock tree 的建置，配合緩衝器插入及調整元件大小來有效縮短時脈延遲、保持零時脈偏 移及降低功率消耗等；進一步考量具有障礙物存在於rectilinear 區域內的障礙物避免(obstacle avoidance) 之X 架構時脈樹建置。完成各個電壓島的時脈樹後，整合系統的多電壓島時脈樹之建構，且因應不同 的叢聚電壓，還須考量位準電壓轉換器(level-shifter converter)的插入，使時脈信號位準驅動達到正確 性，且須規劃插入位準電壓轉換器為最少量，以節省功率消耗。再考量奈米製程對實體效應的影響， 在限制增加時脈延遲與確保零時脈偏移及低功率消耗原則下，結合可製造性設計(DFM)改善單一或多 重電壓島之X 架構時脈繞線之後置處理，如天線效應的偵測與避免(antenna effect detection and avoidance)、光學鄰接效應的檢測與校正(optical effect detection and correction)、冗餘穿孔插入(redundant via insertion)數量的合理化、虛擬金屬層加入(dummy metal/via insertion)、及化學機械研磨(chemical mechanical polishing)所要求之均化佈線密度等。 第二年計劃研究重點：延續第一年獲得的經驗與累積成果，但Divide and Conquer 的方法也面臨 而m 個電壓島就有m!個電壓島時脈樹組合情況，當m 增多時，增加尋找最佳化電源與功率消耗管理 的困難度。第二年採用另一種直接式策略，定義為Top-Down 為主的多重電壓島X 架構時脈網路建置 的問題，先對各個電壓島及評估可能放置位準電壓轉換器(LC)的區域加以標註，再考量這些電壓島區 域及放置位準電壓轉換器(LC)的影響而作整體X-時脈樹建置，藉由時脈延遲(clock delay)、時脈傾斜 誤差(skew)及功率消耗等相關輸出參數來評估，進而規劃最少量位準電壓轉換器的插入及實際調整元 件尺寸大小來有效縮短時脈延遲時間、保持零時脈傾斜誤差及降低功率消耗等，以達到一個系統clock 去驅動多重電壓島時脈信號動作的效能與正確性。同時亦進一步考量多重電壓島的電壓為動態適當範 圍內對時脈延遲(clock delay)、時脈傾斜誤差(skew)及功率消耗的影響等，對X 架構時脈樹作後置的修 正，及結合閘時脈技術控制每個電壓島不同的電壓供應以達到功率消耗管理設計方法。接著考量各種 可製造性設計(DFM)的實體效應，與前一種Divide and Conquer 電壓島型態X-時脈樹建置結果做比 較。最後，將具體延申與考量多重電壓島的時脈樹繞線是否存在著耦合電容和互感等串音干擾，並分 析此干擾對時脈延遲、時脈偏移與功率消耗等影響，提出減低串音干擾的時脈延遲與傾斜誤差比率等抑制方法，對所有test cases 與 benchmarks 作不同情況改善前與改善後的測試與實驗，將此結果作分 析與比較，甚至於作綜合改良。。 綜合連續兩年的所持續規劃研究計畫工作，相信此應用研究成果將對學術界與產業界會有某種程 度的貢獻。
Currently, low power in a SoC (system-on a chip) is one of major requirements. Thus, multiple voltages or cluster voltages in power supply have applied to designs of floorplanning and placement for reducing power consumption. Consequently, there are a number of clock island networks in the environment of multiple voltage islands in a SoC and the clock delay, clock skew, and power consumption dominate the performance and stability of the SoC. We observe number of published papers related to floorplannings and placements that the distribution of voltage islands of their results are always nonuniform. That is, the surrounding of an island is a rectilinear area. How to design a clock synthesized system to construct an X-architecture-based clock tree for driving clock island networks in the environment of multiple voltage islands. Moreover, associate with the effects in physical DFM issues, such as antenna effect reduction, optical proximity correction, redundant vias insertion, dummy metal/via insertion for chemical mechanical polishing, and buffer/lever-shifter insertion combined with gated-clock control for managing power, into the clock synthesized system. Solving the above of them is the purpose of our proposal. The works of first year in this proposal: based on Divide-and-Conquer approach, we define a problem of X-clock tree construction for multiple voltage islands environment. We extend our current works based on voltage-island X-clock tree conststruction and get the initial results in comparison of at least two voltage islands in terms of clock delay, skew, power consumption, and the number of inserted level-shifter converters for improments in advance. Moreover, we define the clock problem in a rectilinear area with some clock sinks and expand our proposed X-clock routing algorithm with a delay model to apply to the problem. The algorithm can be improved for the routing performance by the evaluation in terms of delay, skew, and power. Buffer (or repeater) insertion associated with sizing buffers is used to reduce clock delay and power but keep zero skew. Advancely, the above problem can extend to consider some obstacles in a rectilinear area and the X-clock tree construction needs to have obstacle avoidance. After completing all one-island X-clock trees, then we integrate them to be an X-clock tree appropriated for the multi-island clock network of a SoC. Responsing to multi-voltage supply, level-shifter converters are evaluated to insert into the positions from low-to-high voltages in an X-clock tree for maintaing clock working normally. Moreover, number of level-shifter converters should be controlled to minimum for power reduction. In addition, considering the physical effects of DFM issues in nanometer process, the X-clock tree needs to be corrected at least one of them in post refinement, such as antenna effect detection and avoidance, optical effect detection and correction, redundant via insertion, dummy metal/via insertion, and chemical mechanical polishing. The works of second year: due to Divide-and-Conquer approach may face the complexity of m! combinations for m voltage islands, the power management problem for voltage islands will be derived. Thus, we propose another approach called a directed method. Based on the called Top-Down approach, we define a problem of X-clock tree construction for multiple voltage islands environment. Before making the whole-chip clock tree construction, we evaluate the zones for possiblly inserted level-shifter converter around voltage islands. Then, do the whole-chip X-clock tree construction considering the effects of clock delay, skew, and power consumption due to these preserved converters. Moreover, based on the rules of reducing clock delay and power but keeping zero skew, the number of inserted level-shifter converters should be controlled to be minimal. Extra gated-clock strategy and dynamic voltages for voltage islands can manage power consumption in advance. Furthermore, we associate with the effects in physical DFM issues into our X-clock tree construction of multi-voltage islands for post refinement. Finally, we consider crosstalk between multi-voltage clock islands in advance and propose the solution for crosstalk avoidance. All test cases and benchmarks are used for evaluating our above approaches of X-based clock routing and, furthermore, improve proposed approaches for well-defined comparisons. Approaches of two-year proposal associated with overall DFM issues to X-architecture clock tree construction in the environment of multi-voltage clock islands are valuable to investigate. We believe that proposed approaches to all above problems of X-clock routing synthesis will have valuable contribution for academic and industrial areas. |
